ARM Architecture Study
Welcome to this post, where the exploration of ARM architecture is at the forefront of our discussions. As a professional currently engaged in simulating ARM processors, I’m here to unravel the complexities and innovations of this pivotal technology. ARM’s efficient, low-power consumption design is not just revolutionizing mobile computing; it’s reshaping the way we think about processing power in an array of devices. Join me on this intellectual odyssey as we delve into the nuances of a system that is the bedrock of modern computing efficiency.
Architecture and Microarchitecture
- Architecture is what it has to do, and microarchitecture is how it does it.
Processor Mode
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Most ARM cores have seven basic operating modes (Cortex A and Cortex R)
- Each model has access to its own stack space and a different subset of registers
- Some operations can only be carried out in a privileged mode
- Each mode has its own stack space and a small set of private registers. This feature is called register banking, making the handling of nested exceptions much more efficient from the software point of view.
Mode Description Privileged Mode Exceptional Mode Supervisor (SVC) Entered on hardware reset and when a supervisor call instruction (SVC) is executed Y Y FIQ Entered when a high priority (fast) interrupt is raised Y Y IRQ Entered when a normal priority interrupt is raised Y Y Abort Used to handle memory access violations Y Y Undef Used to handle undefined instructions Y Y System Privileged mode using the same registers as User mode Y User Mode under which most Applications / OS takes run
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Cortex M micro-controller only has two modes
Mode Description Privileged Mode Handler Mode Used for exceptional handlers Y Thread Mode Used for application code
Exceptions
- Definition: Exception is some kind of event which causes an interruption in normal program flow while the system deals with whatever caused that exception.
- Types of exceptions
- Internal: Memory protection fault
- External: Bus error
- Synchronous: SVC instruction
- Asynchronous: Timer interrupt
- What happens when an exception happens:
- Step 1: Save processor status
- Copies CPSR into SPSR_mode
- Stores the return address (PC) in LR_mode
- Step 2: Change processor status for exception
- Model field bits
- ARM or Thumb state
- Interrupt disable bits
- Sets PC to vector address
- Uses the vector table to work out where to find the exception handler
- Vector table has single entry for each exception type, and each entry is an instruction which branches to the relevant handler code
- Step 3: Execute the exception handler
- Step 4: Return to the main application
- Restores CPSR from SPSR_mode
- Restore PC from LR_mode
- Step 1: Save processor status
Two Extensions of architecture
Security Extension (TrustZone)
- Processor provides two world - Secure and Normal
- Secure Monitor acts as a gatekeeper for moving between worlds
Virtualisation Extension
- When implemented, the Virtualization Extensions provide a set of hardware features that support virtualizing the Non-secure state of an ARM VMSAv7 implementation. The basic model of a virtualized system involves:
- a hypervisor, running in Non-secure Hyp mode, that is responsible for switching Guest operating systems
- a number of Guest operating systems, each of which runs in the Non-secure PL1 and PL0 modes
- for each Guest operating system, applications, that usually run in User mode.
Instruction Set
- ARM instruction set
- All instructions are 32 bits long
- Most instructions can be conditionally executed.
- Load / Store instruction set - no direct manipulation of memory content
- Thumb Instruction Set
- 16 bits long, Thumb-2 provides a mixed-length instruction set (16/32 bits long)
- Vector Floating Point (VFP) instructions
- Requires floating point coprocessor and / or software support libraries
- NEON
- a wide SIMD data processing architecture
- Intended for media applications